1. Field of the Invention
This invention relates generally to a system and method for modulating and demodulating a clock signal and digital data onto and from a sinusoidal carrier wave and, more particularly, to a system and method for modulating and demodulating a clock signal and a digital data signal onto and from a sinusoidal carrier wave, where at least one bit of data coincides with each cycle in the carrier wave.
2. Discussion of the Related Art
Digital data is transmitted from a transmitter to a receiver in digital communications systems. The digital data is modulated onto a sinusoidal carrier wave in the transmitter, transmitted, and then demodulated or extracted from the carrier wave in the receiver so that the data can be processed. Various modulation and demodulation schemes are known in the art for modulating the carrier wave to distinguish the zero and one bits in the transmitted signal.
Known modulation techniques include amplitude modulation or on/off keying (OOK) where a change in the amplitude of the carrier wave distinguishes a one bit and a zero bit; frequency-shift keying (FSK) where the frequency of the carrier wave is changed to distinguish a one bit and a zero bit; phase-shift keying (PSK) where polarity changes in the carrier wave provides a 180xc2x0 phase change that is used to distinguish a one bit and a zero bit; and quadrature amplitude modulation (QAM) where the digital data is converted into two-bit symbols which are used to phase modulate the carrier wave. Other types of modulation schemes that combine or are hybrids of those mentioned above are also known in communications systems.
Typically, the transmitter and the receiver employ asynchronous clock signals to control the operation of the various logic circuits. Therefore, the data stream must by synched to the clock signal in the receiver to extract the data. In some systems, a clock signal is transmitted with the data to provide increased clock synchronization capabilities. Further, based on the Nyquist sampling theorem, the sampling rate of the data in the receiver must be at least twice as fast as the data rate. In other words, there must be a minimum of two clock cycles in the receiver for every bit of data. Typically, the data rate is arbitrary relative to the receiver clock signal rate. Thus, there are inherent limitations on how much data can be transmitted at a certain clock rate in the known systems.
Moreover, because the clock signal rate in the receiver is different than the data frequency rate of the transmitted data, there are bandwidth limitations in the system. Particularly, the frequency of the data rate adds sidebands to the center frequency of the carrier wave, which limits the bandwidth in which other carrier waves can be transmitted. Therefore, by not synchronizing the data to the clock, the necessary bandwidth for data transmission is increased. Also, because the carrier waves are typically generated by crystals that have inherent limitations in accuracy, the center frequency of the carrier wave may vary from time to time from an average center frequency.
In accordance with the teachings of the present invention, a system and method for modulating and demodulating a clock signal and a data signal onto and from a common sinusoidal carrier wave is disclosed. In one embodiment, a transmitter is provided where the clock pulse signal is converted to a sine wave that is amplified by a comparator device. The data signal to be transmitted is a gain input to the amplifier, so that if the data signal is high, representing a digital one, the sine wave is amplified by the amplifier, and if the data signal is low, representing a digital zero, the sine wave is not amplified by the amplifier. Therefore, the output of the amplifier is an amplitude modulated sine wave that transmits both the clock signal and the data signal where teach cycle in the sine wave represents a single bit.
In one embodiment for the transmitter above, a receiver circuit is provided for receiving the modulated sine wave and separating a pulsed clock signal and a digital data stream from the sine wave. A first comparator device receives the modulated sine wave and a first predetermined threshold signal, and outputs the pulsed clock signal. A second comparator device receives the modulated sine wave and a second predetermined threshold signal, and outputs a pulse for each one bit transmitted. A third comparator device receives the modulated sine wave, and outputs an inverted modulated sine wave. A fourth comparator devices receives the inverted modulated sine wave and a third predetermined threshold signal, and outputs a pulse signal having positive pulses for each negative portion of the non-inverted modulated sine wave. A flip-flop devices receives the pulse signal from the second comparator device at a set input and the pulse signal from the fourth comparator device at a reset input, where the flip-flop device outputs a pulse each time the second comparator device outputs a pulse so that each cycle of the modulated sine wave identifies a bit in the data stream.
In another embodiment, the transmitter modulates the clock pulse signal with the digital data, where each half-cycle of the sine wave includes a bit. In this embodiment, the clock pulse signal is divided by two before being converted to the sine wave.
A receiver is provided to separate the clock signal and the data signal from the modulated sine wave transmitted by the transmitter. The receiver includes a first comparator device that receives the modulated sine wave from the transmitter and a first predetermined threshold signal. The receiver further includes an inverter that inverts the modulated carrier wave. A second comparator device receives the inverted modulated carrier wave and a second predetermined threshold signal. A first logic gate receives a pulse output signal from the first comparator device and a pulse output signal from the second comparator device. The first logic gate outputs a pulsed clock signal in response to the first and second pulse signals.
A third comparator device receives the modulated carrier wave and a third threshold signal, and a fourth comparator device receives the inverted modulated carrier wave and a fourth threshold signal. A first flip-flop device receives a first set signal from the third comparator device and a first reset signal from the fourth comparator device, where the first flip-flop device outputs the first set signal and the first reset signal resets the first flip-flop device to zero for each pulse of the first reset pulse signal. A fifth comparator device receives the modulated carrier wave and a fifth threshold signal. A second logic gate receives the first set signal at the output of the first flip-flop device and a second pulse signal from the fifth comparator device, where the second logic gate outputs a high signal when both the second pulse signal and the output of the first flip-flop device are high.
The receiver further includes a sixth comparator device that receives the modulated carrier wave and a sixth threshold signal, and a seventh comparator device that receives the inverted modulated carrier wave and a seventh threshold signal. A second flip-flop device receives a second set pulse signal from the seventh comparator device and a second reset pulse signal from the sixth comparator device, where the second flip-flop device outputs the second set pulse signal and the second reset pulse signal resets the output of the second flip-flop device to zero each time the second reset pulse signal is high.
An eighth comparator device receives the inverted modulated sine wave and a eighth threshold signal. A third logic device receives the second set pulse signal from the second flip-flop device and a third pulse signal from the eighth comparator device, where the third logic gate outputs a high signal when both the output of the second flip-flop device and the eighth comparator device are high. A fourth logic gate receives the outputs from the second and third logic gates, and provides a pulse output each time either of the outputs of the second or third logic gate is high. Thus, when the output of the fourth logic gate is high, a digital one is provided, and when the output of the fourth logic gate is low, a digital zero is provided.
In another embodiment, a transmitter is provided for transmitting a sine wave modulated with a digital data stream, where the sine wave includes multiple bits for every cycle. The transmitter includes a divide-by-two counter that receives a square wave clock signal, and divides the clock signal by two. A first inverter inverts the clock signal, and a second inverter inverts the divided clock signal. A square wave-to-sine wave converter receives the inverted and divided clock signal, and converts the square wave clock signal to a sine wave that is modulated with the digital data. An output amplifier receives the sine wave from the converter, which has a gain input that is set by the digital data.
A first logic gate receives the inverted clock signal and the divided clock signal, and outputs a high signal when both the inverted clock signal and the divided clock signal are high. A first flip-flop device receives the output of the first logic gate and the digital data signal, and transfers the data signal to its output when the output of the first logic gate is high. A second logic gate receives the inverted clock signal and the divided clock signal, and outputs a high signal when both the inverted clock signal and the inverted and divided clock signal are high. A second flip-flop device receives the data signal and the output of the second logic gate, and transfers the data signal to its output when the output of the second logic gate is high.
A buffer receives the output of the first flip-flop device and the second flip-flop device, and receives an inverted output of the first logic gate as a clock signal. The buffer simultaneously outputs the outputs of the first flip-flop device and the second flip-flop device each time the inverted output of the first logic gate is high. A summing amplifier, including a voltage divider network, receives both of the outputs of the buffer, where the voltage divider network divides the output of the buffer so that the summing amplifier outputs a first signal level, a second signal level, a third signal level or a fourth signal level depending on the bits being transmitted. The output of the summing amplifier is the gain input to the output amplifier.
A receiver is provided that demodulates the sine wave transmitted by the transmitter described above, and extracts the multiple bits of digital data on every cycle of the sine wave. The receiver employs the same type of logic structure as discussed herein to provide this function. In yet another embodiment, the transmitter modulates the sine wave so that multiple bits are transmitted for every half-cycle of the sine wave. A receiver is provided that is also based on the logic structure discussed herein that extracts the multiple bits of digital data on every half-cycle of the modulated sine wave.
Additional objects, advantages and features of the present invention will become apparent from the following description and appended claims, taken in conjunction with the accompanying drawings.